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| S3C8618/C8615/P8615 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW SAM8 PRODUCT FAMILY Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: -- Efficient register-oriented architecture -- Selectable CPU clock sources -- Idle and Stop power-down mode release by interrupt -- Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. S3C8618/C8615/P8615 MICROCONTROLLERS The S3C8618/C8615/P8615 single-chip 8-bit microcontroller is based on the powerful SAM8 CPU architecture. The internal register file is logically expanded to increase the on-chip register space. The S3C8618/C8615/P8615 have 8/16 K bytes of on-chip program ROM. Following Samsung's modular design approach, the following peripherals were integrated with the SAM8 core: -- Four programmable I/O ports (total 28 pins) -- One 8-bit basic timer for oscillation stabilization and watchdog functions -- One 8-bit general-purpose timer/counter with selectable clock sources -- One 8-bit counter with selectable clock sources, including Hsync or Csync input -- One 8-bit timer for interval mode -- PWM block with seven 8-bit PWM circuits -- Sync processor block (for Vsync and Hsync I/O, Csync input, and Clamp signal output) Figure 1-1. S3C8618/C8615/P8615 Microcontrollers -- Multi master IIC-bus with DDC support. The S3C8618/C8615/P8615 are a versatile microcontroller that is ideal for use in multi-sync monitors or in general-purpose applications that require sophisticated timer/counter, PWM, sync signal processing, and multi-master IIC-bus support with DDC. It is available in a 42-pin SDIP or a 44-pin QFP package. 1-1 PRODUCT OVERVIEW S3C8618/C8615/P8615 FEATURES CPU * SAM8 CPU core -- Two selectable internal clock frequencies -- Hsync (or Csync) input from the sync processor block -- External clock source Pulse Width Modulator * Instruction Set * * 78 instructions IDLE and STOP instructions added for powerdown modes Seven 8-bit PWM modules: -- 8-bit basic frame -- Four push-pull and three n-channel, open-drain output channels -- Selectable clock frequencies: 46.875 kHz at 12 MHz fosc. Sync Processor * * * * Detection of sync input signals (Vsync-I, Hsync-I, and Csync-I) Sync signal separation and output (Hsync-O, Vsync-O, and Clamp-O) Pseudo sync signal output Programmable clamp signal output Memory * * 8/16-Kbyte internal program memory (ROM) 272-byte general-purpose register area Instruction Execution Time * 500 ns minimum (with 12 MHz CPU clock) Interrupts * * * * Nine interrupt sources Nine interrupt vectors Six interrupt levels Fast interrupt processing for a select level General I/O * * * Four I/O ports (total 28 pins): Programmable timer for oscillation stabilization interval control or watchdog timer functions Three selectable internal clock frequencies 8-Bit Basic Timer DDC and Multi-Master IIC-Bus * * Serial peripheral interface Support for display data channel (DDC) Oscillator Frequency * * 6 MHz to 12 MHz external crystal oscillator Interval Max. 12MHz CPU clock - 40C to + 85C Timer/Counters * One 8-bit general-purpose timer/counter with programmable operating modes and the following clock source options: -- Two selectable internal clock frequencies * * One 8-bit timer with interval operating mode One 8-bit counter with the following clock source options: Operating Temperature Range * Operating Voltage Range * 4.5 V to 5.5 V Package Types * 42-pin SDIP, 44-pin QFP 1-2 S3C8618/C8615/P8615 PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7/INT0-INT2 P2.0-P2.7 RESET INT0-INT2 PORT 0 PORT 2 TEST XIN XOUT MAIN OSC INTERNAL BUS PORT 1 I/O PORT and INTERRUPT CONTROL P1.0-P1.3 PWM0 PWM1 * * * PWM6 8-BIT PWM (7-CH) SAM8 CPU PORT3 P3.0-P3.7 Vsync-I Hsync-I Csync-I Vsync-O Hsync-O Clamp-O SYNC PROCESSOR 8/16-KBYTE MASK ROM 272-BYTE REGISTER FILE T0CAP TIMER 0 DDC and Multi master IIC-bus SCL SDA 8-blt Counter (TIMER 1) Interval timer (TIMER 2) T1CK Figure 1-2. Block Diagram 1-3 PRODUCT OVERVIEW S3C8618/C8615/P8615 PIN ASSIGNMENTS P3.1 P3.0 P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3 P0.4/T0CAP P0.5/T1CK VDD P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P2.0/PWM0 P2.1/PWM1 P2.2/PWM2 P2.3/PWM3 P2.4/PWM4 P2.5/PWM5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3C8618/8615 42-SDIP (Top View) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P3.2 VSS2 P3.3 P3.4 P3.5 P3.6 P3.7 RESET XOUT XIN VSS1 P2.7/Csync-I Hsync-I Vsync-I (VCLK) Clamp-O Hsync-O Vsync-O SCL SDA TEST P2.6/PWM6 Figure 1-3. Pin Assignment Diagram (42-SDIP Package) 1-4 S3C8618/C8615/P8615 PRODUCT OVERVIEW P2.1/PWM1 P2.2/PWM2 P2.3/PWM3 P2.4/PWM4 P2.5/PWM5 N.C. P2.6/PWM6 TEST SDA SCL Vsync-O 34 35 36 37 38 39 40 41 42 43 44 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 P2.0/PWM0 P1.3 P1.2 P1.1 P1.0 P0.7 P0.6 VDD P0.5/T1CK P0.4/T0CAP P0.3 S3C8618/8615 44-QFP (Top View) P0.2/INT2 P0.1/INT1 P0.0/INT0 P3.0 P3.1 NC P3.2 VSS2 P3.3 P3.4 P3.5 Figure 1-4. Pin Assignment Diagram (44-QFP Package) Hsync-O Clamp-O Vsync-I Hsync-I P2.7/Csync-I VSS1 XIN XOUT RESET P3.7 P3.6 1 2 3 4 5 6 7 8 9 10 11 1-5 PRODUCT OVERVIEW S3C8618/C8615/P8615 PIN DESCRIPTIONS Table 1-1. S3C8618/C8615/P8615 Pin Descriptions Pin Names P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0-P1.3 Pin Type I/O Pin Description General-purpose, 8-bit I/O port. Share functions include three external interrupt inputs, I/O for timers 0 and 1. You can selectively configure port 0 pins to input or output mode. Circuit Type D-1 SDIP Pin Numbers 3 4 5 6 7 8 10 11 12-15 Shared Functions INT0 INT1 INT2 T0CAP T1CK I/O General purpose, 8-bit I/O port. You can selectively configure port 1 pins to input or push-pull output mode. General purpose, 8-bit I/O port. You can selectively configure port 2 pins to input or output mode. The port 2 pin circuit are designed to push-pull PWM output and Csync signal input. D-1 - P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0-P3.7 I/O D-1 D-1 D-1 D-1 E-1 E-1 E-1 D-1 E 16 17 18 19 20 21 22 31 2, 1, 42, 40-36 30 29 28 27 26 25 24 9 32, 41 33, 34 35 23 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 Csync-I - I/O General-purpose, 8-bit I/O port. You can selectively configure port 3 pins to input or output mode. The pins are sync processor signal I/O and IIC-bus clock and data I/O Hsync-I Vsync-I Clamp-O Hsync-O Vsync-O SCL SDA VDD VSS1, VSS2 XIN, XOUT RESET TEST I I O O O I/O I/O - - I I A A A A A G-3 G-3 - - B - - Power supply pins System clock input and output pins System reset pin Factory test pin input 0 V: normal operation 5 V: factory test mode - - - - NOTE: See `Pin Circuit Diagrams' on next two pages for detailed information on circuit types A, B, D-1, E, E-1,and G-3. 1-6 S3C8618/C8615/P8615 PRODUCT OVERVIEW PIN CIRCUITS Vdd Vss Figure 1-5. Pin Circuit Type A Vdd 280 K Noise Filter RESET Figure 1-6. Pin Circuit Type B (RESET RESET) Data or Other function Vdd Output Output Disable Vss Digital Input or TTL Input Figure 1-7. Pin Circuit Type D-1 1-7 PRODUCT OVERVIEW S3C8618/C8615/P8615 Vdd Typical 47-K Pull-up enable Vdd Data Output Open drain Output Disable Vss Input Figure 1-7. Pin Circuit Type E Vdd Data IN/OUT Open drain Output Disable Vss Input Figure 1-8. Pin Circuit Type E-1 1-8 S3C8618/C8615/P8615 PRODUCT OVERVIEW Output Data Vss Input Figure 1-9. Pin Circuit Type G-3 1-9 S3C8618/C8615/P8615 ELECTRICAL DATA 16 OVERVIEW -- I/O capacitance ELECTRICAL DATA In this section, S3C8618/C8615 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- A.C. electrical characteristics -- Oscillation characteristics -- Oscillation stabilization time -- Schmitt trigger characteristics 16-1 ELECTRICAL DATA S3C8618/C8615/P8615 Table 16-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Output voltage Output current High Output current Low VO I OH Conditions - Type C (n-channel, open-drain) All port pins except VI1 All output pins One I/O pin active All I/O pins active I OL1 I OL2 I OL3 Operating temperature Storage temperature TA TSTG One I/O pin active Total pin current except port 3 Sync-processor I/O pins and IIC-bus clock and data pins - - Rating - 0.3 to + 7.0 - 0.3 to + 10 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 10 - 60 + 30 + 100 + 150 - 40 to + 85 - 65 to + 150 C C Unit V V V mA mA Table 16-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.5 V to 5.5 V) Parameter Input High voltage Symbol VIH1 VIH2 VIH3 Input Low voltage VIL1 VIL2 VIL3 Output High voltage VOH1 VOH2 Conditions All input pins except VIH2 and VIH3 XIN, XOUT TTL input (HsyncI, VsyncI and CsyncI) All input pins except VIL2 and VIL3 XIN, XOUT TTL input (HsyncI, VsyncI and CsyncI) VDD= 4.5 V to 5.5 V IOH = - 8 mA Port 1 only VDD = 4.5 V to 5.5 V IOH = - 2 mA Ports 0, 2, ClampO, H and VsyncO VDD = 4.5 V to 5.5 V IOH = - 6 mA, Port 3 VDD - 1.0 VDD - 1.0 - Min 0.8 VDD VDD - 0.5 2.0 - - Typ - Max VDD VDD VDD 0.2 VDD 0.4 0.8 - V V Unit V VOH3 VDD - 1.0 16-2 S3C8618/C8615/P8615 ELECTRICAL DATA Table 16-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 4.5 V to 5.5 V) Parameter Output Low voltage Symbol VOL1 VOL2 Conditions VDD = 4.5 V to 5.5 V IOL = 8 mA, port 1 only IOL = 2 mA Port 0, 2, ClampO, HsyncO and VsyncO IOL = 6 mA Port 3, SCL and SDA VIN = VDD All input pins except XIN, XOUT VIN = VDD XOUT only VIN = VDD XIN only VIN = 0 V All input pins except XIN, XOUT VIN = 0 V; XOUT only VIN = 0 V; XIN only VOUT = VDD All output pins except port 1 VOUT = 0 V VIN = 0 V; VDD = 4.5 V to 5.5 V Port 3 VIN = 0 V; VDD = 4.5 V to 5.5 V RESET only Supply current (note) Min - Typ - Max 0.4 0.4 Unit V VOL3 Input High leakage current ILIH1 0.4 - - 3 A ILIH2 ILIH3 Input Low leakage current ILIL1 - 2.5 - - 6 - 20 20 -3 A and RESET ILIL2 ILIL3 Output High leakage current Output Low leakage current Pull-up resistor ILOHL ILOL RL1 - - 2.5 - - 20 - -6 - - 47 - 20 - 20 3 -3 80 A A k RL2 150 280 480 IDD1 IDD2 VDD = 4.5 V to 5.5 V 12 MHz CPU clock Idle mode; VDD = 4.5 V to 5.5 V 12 MHz CPU clock Stop mode; VDD = 5.0 V - 15 5 30 10 mA IDD3 1 10 A NOTE: Supply current does not include drawn internal pull-up resistors and external loads of output. 16-3 ELECTRICAL DATA S3C8618/C8615/P8615 Table 16-3. Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode Stop mode, VDDDR = 2.0 V Min 2 - Typ - - Max 6 5 Unit V A NOTES: 1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped. 2. Supply current does not include drawn through internal pull-up resistors and external output current loads. RESET OCCURS OSCILLATION STABILIZATION TIME NORMAL OPERATING MODE STOP MODE DATA RETENTION MODE VDD VDDDR EXECUTION OF STOP INSTRUCTION RESET NOTE: tWAIT is the same as 4096 x 32 x 1 / fOSC . tWAIT Figure 16-1. Stop Mode Release Timing When Initiated by a Reset Table 16-4. Input/Output Capacitance (TA = - 40 C to + 85 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min - Typ - Max 10 Unit pF 16-4 S3C8618/C8615/P8615 ELECTRICAL DATA Table 16-5. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.5 V to 5.5V) Parameter Noise Filter Symbol tNF1H, tNF1L tNF2 Conditions P0.2-P0.0, T0CAP and T1CK (RC delay) RESET only (RC delay) Min 300 800 Typ - - Max - - Unit ns 1 tCPU tNF1L tNF2 tNF1H 0.8 VDD 0.2 VDD NOTE: The unit tCPU means one CPU clock period. Figure 16-2. Input Timing Measurement Points for P0.0-P0.2, T0CAP and T1CK 16-5 ELECTRICAL DATA S3C8618/C8615/P8615 Table 16-6. Oscillation Characteristics (TA = - 40 C + 85 C) Oscillator Main crystal or ceramic Clock Circuit C1 Conditions VDD = 4.5 V to 5.5 V Min 6 Typ - Max 12 Unit MHz XIN XOUT C2 External clock (main) XIN XOUT VDD = 4.5 V to 5.5 V 6 - 12 MHz NOTE: The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannot select a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values. Table 16-7. Recommended Oscillator Constants (TA = - 40 C + 85 C, VDD = 4.5 V to 5.5 V) Manufacturer Product Name Load Cap (pF) C1 TDK FCR8.0MC5 (note) FCR8.0M5 CCR8.0MC5 (note) NOTE: On-chip C: 30 pF 20 % built in. Oscillator Voltage Range (V) MIN 4.5 4.5 4.5 MAX 5.5 5.5 5.5 Remarks C2 - 33 - - 33 - On-chip C Leaded Type Leaded Type On-chip C SMD Type Table 16-8. Oscillation Stabilization Time (TA = - 40 C + 85 C, VDD = 4.5 V to 5.5 V) Oscillator Crystal Ceramic External clock Test Condition VDD = 4.5 V to 5.5 V VDD = 4.5 V to 5.5V XIN input High and Low level width (tXH, tXL) Min - - 25 Typ - - - Max 20 10 500 ns Unit ms NOTE: Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is released. 16-6 S3C8618/C8615/P8615 ELECTRICAL DATA 1 / f OSC tXL tXH XIN VDD - 0.5 V 0.4 V Figure 16-3. Clock Timing Measurement Points for XIN Vout VDD A : 0.2 V DD B : 0.4 V DD C : 0.6 V DD D : 0.8 V DD VSS Vin A B C D Figure 16-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input) 16-7 S3C8618/C8615/P8615 MECHANICAL DATA 17 OVERVIEW 42 14.00 0.2 MECHANICAL DATA The S3C8615 microcontroller is available in a 42-pin SDIP package (Samsung part number 42-SDIP-600) and a 44-QFP package (Samsung part number 44-QFP-1010B). 22 0 ~ 15 42-SDIP-600 #1 21 0.25 +0.1 - 0.0 5 3.50 0.2 (1.77) 0.50 0.1 1.00 0.1 1.778 NOTE: Dimensions are in millimeters. Figure 17-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600) 3.30 0.3 0.51MIN 5.08MAX 39.10 0.2 15.24 17-1 MECHANICAL DATA S3C8618/C8615/P8615 13.20 0.3 10.00 0.2 0~8 0.15 +0.10 - 0.05 13.20 0.3 10.00 0.2 44-QFP-1010B 0.10 MAX #44 0.05 MIN 2.05 0.10 #1 0.80 0.35 - 0.05 (1.00) +0.10 2.30 MAX NOTE: Dimensions are in millimeters. Figure 17-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B) 17-2 0.800.20 S3C8618/C8615/P8615 S3P8615 OTP 18 OVERVIEW S3P8615 OTP The S3P8615 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3P8615 microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P8615 is fully compatible with the S3C8618/C8615, both in function and in pin configuration. Because of its simple programming requirements, the S3P8615 is ideal for use as an evaluation chip for the S3C8618/C8615. P3.1 P3.0 P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3 P0.4/T0CAP P0.5/T1CK VDD/VDD P0.6 P0.7 SCLK/P1.0 SDAT/P1.1 P1.2 P1.3 P2.0/PWM0 P2.1/PWM1 P2.2/PWM2 P2.3/PWM3 P2.4/PWM4 P2.5/PWM5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3P8618/8615 42-SDIP (Top View) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P3.2 VSS2/VSS2 P3.3 P3.4 P3.5 P3.6 P3.7 RESET/RESET RESET XOUT XIN VSS1/VSS1 P2.7/Csync-I Hsync-I Vsync-I (VCLK) Clamp-O Hsync-O Vsync-O SCL SDA TEST/VPP P2.6/PWM6 NOTE: The bolds indicate an OTP pin name. Figure 18-1. S3P8615 Pin Assignments (42-SDIP Package) 18-1 S3P8615 OTP S3C8618/C8615/P8615 P2.1/PWM1 P2.2/PWM2 P2.3/PWM3 P2.4/PWM4 P2.5/PWM5 N.C. P2.6/PWM6 VPP/TEST SDA SCL Vsync-O 34 35 36 37 38 39 40 41 42 43 44 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 P2.0/PWM0 P1.3 P1.2 P1.1/SDAT P1.0/SCLK P0.7 P0.6 VDD/VDD P0.5/T1CK P0.4/T0CAP P0.3 S3C8618/8615 44-QFP (Top View) P0.2/INT2 P0.1/INT1 P0.0/INT0 P3.0 P3.1 NC P3.2 VSS2/VSS2 P3.3 P3.4 P3.5 Figure 18-2. S3P8615 Pin Assignments (44-QFP Package) 18-2 Hsync-O Clamp-O Vsync-I Hsync-I P2.7/Csync-I VSS1/VSS1 XIN XOUT RESET/RESET RESET P3.7 P3.6 1 2 3 4 5 6 7 8 9 10 11 S3C8618/C8615/P8615 S3P8615 OTP Table 18-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P1.1 Pin Name SDAT Pin No. 13 (*30) During Programming I/O I/O Function Serial DATa Pin (Output when reading, Input when writing) Input & Push-pull Output Port can be assigned Serial CLocK Pin (Input Only Pin) EPROM Cell Writing Power Supply Pin (Indicates OTP Mode Entering) When writing 12.5 V is applied and when reading 5V is applied.(Option) Chip Initialization Logic Power Supply Pin. VDD should be tied to 5 V during programming. P1.0 TEST SCLK VPP (TEST) 12 (*29) 23 (*41) I I RESET VDD/VSS1/VSS2 RESET VDD/VSS/VSS 35 (*9) 9 / 32 / 41 (*26 / 6 / 15) I I NOTE: * means the 44-QFP OTP pin number. Table 18-2. Comparison of S3P8615 and S3C8618/C8615 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 4.5 V to 5.5 V VDD = 5 V, VPP (TEST)=12.5V 42-SDIP, 44-QFP User Program 1 time 42-SDIP, 44-QFP Programmed at the factory S3P8615 16 K byte EPROM S3C8618/C8615 16 K byte mask ROM 4.5 V to 5.5V OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P8615, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 18-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 ADDRESS (A15-A0) 0000H 0000H 0000H 0E3FH R/W W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection MODE NOTE: "0" means Low level; "1" means High level. 18-3 S3P8615 OTP S3C8618/C8615/P8615 D.C. ELECTRICAL CHARACTERISTICS Table 18-4. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 4.5 V to 5.5 V) Parameter Input High leakage current Symbol ILIH1 ILIH2 ILIH3 Input Low leakage current ILIL1 Conditions VIN = VDD; All input pins except XIN, XOUT VIN = VDD; XOUT only VIN = VDD; XIN only VIN = 0 V; All input pins except XIN, XOUT and RESET VIN = 0 V; XOUT only VIN = 0 V; XIN only VOUT = VDD VOUT = 0 V Normal operating mode; 12 MHz CPU clock IDD2 IDD3 Data retention supply voltage Data retention supply voltage VDDDR IDDDR IDLE mode; 12 MHz CPU clock Stop mode; VDD = 5.0 V Stop mode Stop mode; VDDDR = 2V - 2 - 5 1 - - 10 10 6 5 A V A 2.5 - 6 - Min - Typ - Max 3 20 20 -3 A Unit A ILIL2 ILIL3 Output High leakage current Output Low leakage current Supply current ILOH1 ILOL1 IDD1 - - 2.5 - - - - -6 - - 15 - 20 - 20 3 -3 30 A A mA 18-4 S3C8618/C8615/P8615 S3P8615 OTP START Address= First Location VDD =5V, V PP=12.5V x=0 Program One 1ms Pulse Increment X YES x = 10 NO FAIL Verify Byte Verify 1 Byte FAIL Last Address NO Increment Address VDD = VPP= 5 V FAIL Compare All Byte PASS Device Failed Device Passed Figure 18-3. OTP Programming Algorithm 18-5 |
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